Semiconductor structure useful in a self-aligned contact etch and method for making same

ABSTRACT

A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to semiconductorstructures and methods of forming semiconductor structures, and, moreparticularly, to structures and methods of forming structures useful inself-aligned contact etches.

[0003] 2. Description of Related Art

[0004] In the fabrication of multilayered integrated circuits, it isfrequently desirable to etch a vertical opening in a layer overlying asubstrate to form electrical contacts to the substrate. This commonlyrequires etching through several layers of different types of overlyingmaterial. To assure that electrical contact is made with only thesubstrate, other structures, such as transistor gates, are enclosed ininsulating sidewalls and caps that provide a degree of correction orself-alignment to the etch process. One problem in the prior art is thatthe etching process attacks these insulating surfaces to some extent. Ifthe etch penetrates the insulating surfaces, subsequent deposition ofconductive material will short-circuit different layers of the device.

[0005] FIGS. 1-4 illustrate various stages of the process in the priorart. The drawings represent vertical sections of the same semiconductorstructure 10. FIG. 1 shows the structure 10 prior to the contact etch.The goal of the process is to attach a contact to the lower substrate12, typically a semiconductor substrate, in a location 13 positionedadjacent two multilayered structures 14. The multilayered structures 14can be, for example, comprised of doped polysilicon 16 and silicide 18.The silicide 18 is typically a tungsten silicide. Both the polysilicon16 and silicide 18 are conductive and together may form, for example, atransistor gate. Insulative layers, such as caps 20 and sidewalls 22formed of nitride, cover the surfaces and sides of the conducting layers16 and 18. A uniform, conformal SiO₂ coating 24 covers both the outersurface of the raised structures 14 and the underlying substrate 12. TheSiO₂ layer 24 is typically produced by a low pressure chemical vapordeposition (LPCVD) of tetraethyloxysilane (TEOS). The SiO₂ layer 24conforms itself to the underlying topography. A layer ofborophosphosilicate glass (BPSG), or another doped oxide such asphosphosilicate glass (PSG), 26 covers the SiO₂ layer 24.

[0006] The SiO₂ layer 24 acts as a barrier resistant to the migration ofdopants from the BPSG layer 26 into the multilayered structures 14 andsubstrate 12. The prior art has unsuccessfully attempted to use“breadloafed” oxide deposits as diffusion barriers between BPSG andunderlying conducting regions. These oxides have proven to be inferiorfor such purposes when they are the only insulator between the BPSGlayer 26 and the transistor gate 16, 18. The breadloafing depositiontechnique produces a coating that does not conform to the underlyingtopography, producing an oxide that is thicker at upper corners ofstructures such as transistor gates, and which is undesirably thin inlower corners and bottoms of tight areas. Accordingly, the prior art hasavoided the use of breadloafed oxides in favor of more desirableconformal oxides.

[0007]FIG. 2 shows the structure 10 after a successful vertical etchthrough the BPSG 26 and the SiO₂ 24 layers. The insulating caps 20 andsidewalls 22 act to guide, or self-align, the etch process to form anopening 28 that makes contact with the underlying substrate 12 on acontact area 30 situated adjacent the multilayered structures 14. Thisis accomplished by using a chemistry that will etch oxides at a muchfaster rate than nitrides, such as a low pressure mixture of CHF₃—Ar—CF₄with the additive CH₂F₂. The subsequent deposition of a conductingmaterial, such as a metal, onto the surface of the semiconductorstructure 10 forms a contact that fills the opening 28. The etchingprocess also invariably erodes away some of the sidewall material 22,leaving a thinner insulating layer 32. To avoid a short-circuit betweenthe conducting regions 18, 16 and the contact, the etch must not breakthrough the sidewalls 22 of FIG. 1. The original sidewall protection ofthe silicide conductive layer 18 is thinnest along line 34 in FIG. 1,and thus the risk of sidewall breach is highest in that region. Afteretching, the sidewall insulation 22 is thinnest near the point 36 inFIG. 2.

[0008]FIG. 3 shows an unsuccessful etch of the semiconductor structure10 in which a sidewall breach 38 exposes the conducting region 18. Thesidewall breach 38 will result in a short-circuit when the conductivematerial is subsequently deposited in the contact opening 28. The breachoccurred in the region where the original sidewalls were thinnest. Thisfailure can happen due to over-etching, misalignment of the etchingmask, or by choosing an etchant that is not suitably selective foroxides. Sidewall breach is a problem for the prior art and isexacerbated by the continual evolution to smaller semiconductorstructures. That is, as the structures become smaller, sidewallstructures become even thinner and, thus, more prone to sidewall breach.

[0009] One method used by the prior art to avoid sidewall breachinvolves etching vertical openings that are narrower than the spacebetween adjacent sidewalls 32. The use of narrower openings, however,puts undesirable constraints on photomask alignment. Furthermore,alignment problems are exacerbated as the semiconductor structures areminiaturized. Smaller semiconductor structures have a smaller margin oferror in alignment and in timing of the duration of the etching process.

[0010]FIG. 4 illustrates an alternative prior art method to avoidsidewall breaches. This procedure reduces the risk of sidewall breach byemploying a two-step etching process. The starting structure is similarto that of FIG. 1. The first etch proceeds anisotropically underconditions assuring that the BPSG layer 26 is removed more rapidly thanthe SiO₂ layer 24. This step terminates before the SiO₂ layer 24 iscompletely removed. The second step is an isotropic wet etch, which usesan etchant that removes the SiO₂ layer 24 more rapidly than the nitridesidewalls 22. Accordingly, the second etch exposes the conductivesubstrate 44 before a sidewall breach occurs. This two-step etch processis undesirable because it is time consuming, costly and unnecessarilycomplicates the process, increasing the risk that errors will occur. Theisotropic etch also runs the risk of laterally etching the BPSG layer 26making the critical dimension W too wide.

[0011] The present invention is directed to overcoming, or at leastreducing the effects of, one or more of the problems set forth above.

SUMMARY OF THE INVENTION

[0012] The invention includes an apparatus having a semiconductorsubstrate and a contact area on one surface of the substrate. At leastone structure is formed on the surface of the substrate adjacent thecontact area. An insulative layer extends over at least a portion of thestructure. A layer of doped oxide also extends over at least a portionof the structure. An intermediate insulative layer is deposited betweenthe structure and the layer of doped oxide. The intermediate layer has agenerally breadloafed form in an area adjacent the structure. Theintermediate layer is also resistant to the migration of dopants fromthe layer of doped oxide into the structure and substrate.

[0013] The invention includes a method for making a semiconductordevice. The method comprises forming a semiconductor substrate. At leastone structure is formed on the surface of the substrate. A firstinsulative layer is formed over at least a portion of the structure. Asecond insulative layer, having a generally breadloafed form, is formedover at least a portion of the structure and substrate. The secondinsulative layer is a also a barrier to the migration of dopants. Alayer of doped oxide is formed over the first and second insulativelayers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The foregoing and other advantages of the invention will becomeapparent upon reading the following detailed description and uponreference to the drawings in which:

[0015]FIG. 1 is a diagrammatic cross-sectional view of a semiconductorwafer of the prior art before the anisotropic etching has beenperformed;

[0016]FIG. 2 is a diagrammatic cross-sectional view of the semiconductorwafer of FIG. 1 after anisotropic etching has been performed;

[0017]FIG. 3 is a diagrammatic cross-sectional view of the semiconductorwafer of FIG. 1 prior art showing the problem of sidewall breach;

[0018]FIG. 4 is a diagrammatic cross-sectional view of a semiconductorwafer after the first etch of a two-step process of the prior art;

[0019]FIG. 5 is a diagrammatic cross-sectional view of one embodiment ofa semiconductor wafer employing the invention before a self-alignedcontact (SAC) etching process;

[0020]FIG. 6 is a diagrammatic cross-sectional view of the semiconductorwafer of FIG. 5 after the anisotropic SAC etching has been performed;

[0021]FIG. 7 is a diagrammatic cross-sectional view of the semiconductorwafer of FIG. 6 after a conductive contact layer has been applied; and

[0022]FIG. 8 is a diagrammatic cross-sectional view of a secondembodiment of the invention using nitride breadloafed layers before theSAC etching process.

[0023] While the invention is susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and will be described in detail herein. However,it should be understood that the invention is not intended to be limitedto the particular forms disclosed. Rather, the intention is to cover allmodifications, equivalents and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0024] The following examples are included to demonstrate preferredembodiments of the invention. It should be appreciated by those skilledin the art that the techniques disclosed in the examples that followrepresent techniques discovered by the inventor to function well in thepractice of the invention, and thus can be considered to constitutepreferred modes for its practice. However, those skilled in the artshould, in light of the present disclosure, appreciate that many changescan be made in the specific embodiments disclosed herein and stillobtain a like or similar result without departing from the spirit andscope of the invention.

[0025] Referring to FIG. 5, a portion of a semiconductor wafer 50 isshown. The wafer 50 has a substrate 52 with a top surface 54 on whichconventional patterning and etching has formed two multilayeredstructures 56. The substrate 50 may be any suitable material known tothe art and may be a wafer or a previously deposited oxide layer. Themultilayered structures 56 contain various conductive layers 58, 60 ofdoped polysilicon and silicide respectively. In one embodiment, thesilicide layer 60 is tungsten silicide. The multilayered structures 56illustrated herein are transistor gates; however, the scope of theinvention includes all manner of integrated circuit structuresregardless of construction. The type of integrated circuit structure isimmaterial to the practice of the instant invention.

[0026] The layers 58 and 60 of the structures 56 are covered by aninsulator or insulative layer. In a preferred embodiment, the insulativelayer includes caps 62 and sidewalls 64 of nitride. The nitride caps andsidewalls 62, 64, are the result of prior depositions and etchings usingknown techniques. The caps 62 and sidewalls 64 can be formed from otherinsulative materials, such as SiO₂. In that case, the selected firstetch process, described below, must be faster in a doped oxide layer 74than in the insulative material chosen for the caps 62 and sidewalls 64.In the embodiments described herein, the doped oxide can be for exampleborophosphosilicate glass (BPSG) or another doped oxide, such asphosphosilicate glass (PSG). A series of depositions has covered thesurfaces of the layered structures 56 and the substrate 54 with twolayers 66, 70. While the layers 66, 70 are illustrated with layer 70overlaying layer 66, it is envisioned that the order could be reversedwithout departing from the spirit and scope of the invention.

[0027] The first layer 66 is a generally conformal, undoped layer ofSiO₂ having a thickness in the range of about 100-300 Angstroms. Oneknown method for depositing the conformal layer 66 of SiO₂ uses a lowpressure chemical vapor deposition of tetraethyloxysilane (TEOS). In apreferred embodiment, the conformal oxide layer 66 is formed byintroducing TEOS vapor into a furnace containing the wafer at a pressureof about 600 mtorr, at a temperature of about 675° C. and for a periodof about 10 minutes. Usable ranges of the conditions for the furnacedeposition of TEOS vapor include pressures from 400 to 800 mtorr andtemperatures from 650 to 750° C.

[0028] The second layer 70 is a breadloafed layer of SiO₂ or nitride.The layer 70 is not conformal. That is, the thickness of the layer 70varies with variations in the underlying topography to produce abreadloaf like cross section 72. The breadloafed layers 70 are thickerin regions 72 adjacent vertical sufaces of the multilayered structures56 that are distant from the top surface 54 of the substrate 52. As isdescribed below, the exact amount of thickening of the breadloafed layer72 is preferably related to dimensions of and distances between theunderlying multi-layered structures 56. In particular, the layer 70 isthicker adjacent the upper corner area of the underlying nitridesidewalls 64. After the deposition of the breadloafed oxide layer 70, astructure is present on the sides of layered structures 56 that has athickened region 72 along the upper corners of the original nitridesidewalls 64. Thus, layers 66, 70 combine to provide sidewalls that arethicker at the top corners than the original SiO₂ layer shown in FIG. 1as layer 24.

[0029] The thickness of the breadloafed layer 70 is dependent on thedistance between the outside edges of the two sidewalls 64. Formultilayered structures 56 having a height of about 6500 angstroms, itis preferable that the opening between the outer corners 72 be about 600and 900 angstroms for oxide and nitride breadloafed layers respectively.When the breadloafed layer 70 is made of undoped oxide as opposed tonitride it must be thicker, because about 300 angstroms of the oxidewill be contaminated by dopants from a subsequently applied layer ofBPSG 74 during reflow heating. The contaminated part of the SiO₂ layer70 etches more like BPSG than like undoped SiO₂. Therefore, breadloafedlayers 70 of undoped oxide afford less protection than layers of nitrideof equal thickness. If the distance between the sidewalls 64 is 2,000and 2,500 angstroms at the top and bottom respectively and if theconformal layer 66 is 300 angstroms thick, it is preferable that theopening be about 600 angstroms wide after the breadloafed layer 70 isdeposited. For these dimensions, a breadloaf layer 70 of SiO₂ shouldhave a thickness of about 400 angstroms measured at the corners 72. Inthe general case, the deposition thickness of the breadloaf structure70, 72 will dependent on the size of the opening between themultilayered structures 56 and the material used for the breadloaf layer70.

[0030] Preferably, plasma deposition of low pressure silane gas is usedto produce the breadloafed oxide layer 70. An Applied Materials 5000DSystem is used to perform the deposition. Examples of conditions thatresult in sufficiently breadloafed deposits are: pressure of 2.2 torr,205 watts RF power, 400° C. susceptor (347° C. wafer), 65 sccm SiH₄, and2400 sccm N₂O. For these conditions, the deposition rate isapproximately 97.4 Angstroms per second. Thus, a 1000 Angstrom widebreadloafed deposit takes approximately 10 seconds of running time. Ofcourse, the exact deposition time depends on the size of any underlyingstructures in the device.

[0031] The parameters for the plasma deposition of silane gas are onlyexamples. The values of various parameters such as RF power and pressurecan be varied. For example, the deposition rate for the breadloafedlayer 70 can be decreased by reducing the gas flow rates. Likewise,increasing pressure and/or RF power tends to enhance the breadloafeffect. Usable parameter ranges for depositing the breadloafed layerare: pressure of about 1.98-2.42 torr, 184-226 watts RF power, 360-440°C. susceptor, 58-72 sccm SiH₄, and 2160-2640 sccm N₂O.

[0032] A doped oxide layer 74 of, for example, BPSG covers the lowerlayers 66, 70 to a thickness of about 8,000-10,000 angstroms above thelower layers 66, 70. The undoped oxide layer 66 acts as a barrierresistant to the migration of dopants from the BPSG layer 74 into theunderlying multilayered structures 56 and substrate 52. The dopantpercentages in the BPSG are determined from the known thermal propertiesand the reflow rates desired for the BPSG layer 74. One preferredcomposition has 6.9% phosphorous and 3.8% boron by weight. One knownmethod of fabrication uses chemical vapor deposition of silane gas inthe presence of oxygen. The process is carried out at 450° C. at eitherlow or atmospheric pressure. The addition of diborane and phosphenegases to the other gases produces the dopants in the BPSG layer 74.

[0033] Referring to FIG. 6, a vertical opening 76 has been masked andetched to provide an access to the lower substrate 52 along the contactarea 78. The opening 76 is the result of one or more anisotropic dryetches in the vertical direction. The first and deepest etch generallyremoves BPSG faster than undoped oxides or nitride. The selectivity ofthe first etch and the increased width of the upper sidewalls, at theregion 72, combine to diminish the risk of sidewall breach. The firstetch is timed to terminate after either undoped oxide layer 66 or 70 isexposed over the surface 78. One embodiment uses an Applied Materials5000 reactor to perform this etch. Appropriate conditions for theanisotropic etch are: pressure of about 45 mtorr, 900 watts RF power, 40gauss, 20 sccm CF₄, 45 sccm CHF₃, 20 sccm CH₂F₂, 80 sccm Ar, and 9000mtorr He backside pressure. These conditions result in an etch rate ofabout 50 angstroms of BPSG per second and a selectivity ratio of BPSG toundoped oxide of at least 10:1. The selectivity ratio of BPSG to undopedSiO₂ can be varied by changing the concentration of CH₂F₂. Usable rangesfor the anisotropic etch conditions include: pressure 35-55 mtorr,800-1000 watts RF power, 20-60 gauss, 10-30 sccm CF₄, 35-55 sccm CHF₃,16-24 sccm CH₂F₂, 60-100 sccm Ar, and 4,500-10,00 mtorr He backsidepressure.

[0034] Since the first etch is selectively more rapid in BPSG, a secondetch that has, at least, similar etch rates in undoped oxide and BPSG isgenerally necessary to assure that the contact region 78, FIG. 5, iscleared of the undoped oxide layers 66, 70 (nitride layers in alternateembodiments 84 of FIG. 8). Before the second etch, an O₂ clean etch maybe used to remove any polymer from the otherwise exposed undoped SiO₂layers 66, 70 (nitride layers in alternate embodiments 84 of FIG. 8).The polymer results from the previous BPSG to undoped oxide selectiveetch process. The presence of polymer would hamper the ability of thesecond etch to remove the undoped SiO₂ layers 66, 70 (nitride layers inalternate embodiments 84 of FIG. 8). Appropriate conditions for the O₂clean etch are: pressure of about 50 mtorr, 300 watts RF power, 40gauss, 30 sccm O₂, and 9000 mtorr He backside pressure. These conditionsresult in an etch rate of about 10 angstroms of the polymer per second.Usable ranges for the conditions of the O₂ clean etch are: pressure ofabout 40-60 mtorr, 200-400 watts RF power, 20-60 gauss, 15-45 sccm O₂,and 4,500-10,000 mtorr He backside pressure. Once the polymer has beenremoved, where necessary, the undoped SiO₂ layers 66, 70 can be etchedaway, thereby exposing the substrate surface 78. The second etch is ananisotropic dry etch having a lower selectivity of BPSG to undoped SiO₂and/or nitride than in the first etch. Appropriate condition for thisdry etch are: pressure of about 200 mtorr, 600 watts RF power, 100gauss, 20 sccm CF₄, 30 sccm CHF₃, and 9000 mtorr He backside pressure.These conditions result in an etch rate of about 54 angstroms of undopedSiO₂ per second. Usable ranges for the conditions of the dry etch are:pressure of about 100-300 mtorr, 400-800 watts RF power, 40-100 gauss(preferably not above 100 gauss), 10-40 sccm CF₄, 15-45 sccm CHF₃, and4,500-10,000 mtorr He backside pressure. Both the O₂ clean etch and thesecond etch, having a low selectivity of BPSG to undoped oxide and/ornitride are short enough to cause a minimal amount of loss of undopedSiO₂ or nitride along the corners 72, sidewalls 64 and caps 62, but longenough to remove the undoped SiO₂ layers 66, 70 from the bottom of thecontact 78 exposing the substrate 52.

[0035] The problem of dopant migration from the BPSG into the underlyingundoped layers 66, 70 can change the etching rates of the underlyinglayers 66, 70 during the above-described first etch. Thus, it may bepreferable to deposit the undoped oxide layers 66, 70 in a specificorder. The first deposition would be the breadloafed layer. The seconddeposition would be the 100-300 angstrom conformal layer which therebyoverlays the breadloafed layer. The conformal layer can be thicker aslong as the opening between the multilayered structures 56 is not closedoff. This inverts the order of the two undoped oxide layers 66, 70 ofFIG. 5. The last deposition would be the BPSG layer 74. With thisarrangement, the conformal layer and not the breadloafed layer risksbeing contaminated by dopant migration during the subsequent reflowheating of the BPSG layer. During the above-described first etch, thecontaminated conformal oxide layer would be removed at close to the samerate as the BPSG layer, but the underlying breadloafed layer wouldretain its undoped form and etch at a slower rate. For this arrangement,the breadloafed layer still provides protection from sidewall breacheven after dopant migration. The second deposition of the conformallayer can be thinner as long as dopant migration from the BPSG layer 74does not go through the underlying breadloafed layer to contaminate theconductive layers 58, 60 or the substrate 52.

[0036] An alternative etch process employs a two-step dry/wet etch. Thefirst etch is vertical and dry. The first etch is terminated before theundoped oxide layer 66 (see FIG. 5) is removed, lowering the risk of abreach through the nitride sidewall 64. Next, an isotropic wet etch isperformed with an aqueous solution comprising hydrogen fluoride andhaving about 10% by weight of a surfactant. Example surfactants can beanionic, cationic, amphoteric, and nonionic. One preferred solutioncomprises aqueous solution of HF having 0.5% by weight fluorine andabout 10% by weight tetra methyl ammonium hydroxide. Usable ranges forthe aqueous solution of HF have about 0.3-0.8% by weight fluorine andabout 8-12% by weight tetra methyl ammonium hydroxide. The surfactantchanges the etching rates, giving a greater etch rate for the undopedoxide layers 70, 66 than for BPSG 74. The breadloafed layer 70 enhancesthe thickness of undoped oxide on sidewalls 72, as compared to thecontact area 78. Thus, the isotropic wet etch can be timed so that thecontact area 78 is substantially cleared of oxide before a breach of thethickened insulative protective layer composed of conformal 65 andbreadloafed 70 layers, sidewalls 64, and caps 62.

[0037] For thick BPSG layers 74, it may be preferable to precede theabove-described etching processes by another dry etch having a highselectivity for BPSG. The new etch is terminated at or before the timethat it reaches the top of the breadloafed layer 70 of FIG. 5. In anApplied Materials 500 Reactor, exemplary conditions are: pressure of 105mtorr, 900 watts RF power, 90 gauss, 23 sccm CF₄, 50 sccm CHF₃, 110 sccmAr, 30 sccm N₂, and 9000 mtorr He backside pressure. These conditionsgive an etch rate of about 65 angstroms of BPSG per second. Usableparameter ranges for the dry etch having a high selectivity for BPSGare: pressure of about 80-130 mtorr, 700-1100 watts RF power, 60-100gauss, 18-30 sccm CF₄, 30-60 sccm CHF₃, 95-125 sccm Ar, 10-50 sccm N₂,and 4,500-10,000 mtorr He backside pressure. Normally, this etch isfollowed by one of the above-mentioned two-step etch processes.

[0038] Referring to FIG. 7, the wafer 50 of FIG. 6 is shown with a layerof conductive material 80 deposited thereover. The conductive material80 substantially fills the opening 76 to form an electrical connectionwith the contact area 78. The conductive material 80 can be formed fromany of a variety of materials known to those skilled in the art,including but not limited to polysilicon, tungsten, and aluminum,tungsten silicide, and titanium silicide.

[0039] Referring now to an alternative embodiment illustrated in FIG. 8,the undoped oxide layers 70, 66 of FIG. 5 are replaced by a singlenitride deposit 84. Through the use of a plasma deposition process, thenitride layer 84 has been deposited in a breadloaf form. The singlebreadloafed nitride layer 84 acts both as a barrier resistant to dopantmigration from BPSG and as a stop for the anisotropic contact etch.Thus, the breadloafed nitride layer 84 also replaces the oxide layer 66of FIG. 5.

[0040] The nitride deposition is performed on an Applied Materials 5000DSystem with the following recipe parameters: 4.2 torr, 735 watts RFpower, 400° C. susceptor (375° C. wafer), 275 sccm SiH₄, 4000 sccm N₂,and 120 sccm NH₃. The deposition rate is about 123 Angstroms per second.A usable range for the recipe parameters includes: 3.78-4.62 Torr,661-809 watts RF power, 360-440° C. susceptor, 247-303 sccm SiH₄,3,600-4,400 sccm N₂, and 108-132 sccm NH₃. A preferred thickness for thenitride breadloafed layer has been described in the alternate embodimenthaving a breadloafed layer of undoped oxide 70, FIG. 5. A deposition ofnitride, of the described thickness, also suffices to form a diffusionbarrier against dopant contamination from the overlying doped BPSGoxide.

[0041] The nitride breadloafed layer 84, as well as the sidewalls 64 andcaps 62 together act as a stop for the anisotropic etch. The etch rateshould be faster for BPSG than for nitride. As a result of thebreadloafing technique, such an etch can again be timed to substantiallyclear the contact area 78 without breaching the sidewalls 64, caps 62,or breadloafed layer 84. The preferred series of etches are theabove-described dry etches for the embodiment using an undoped SiO₂breadloafed layer 70. For that embodiment, the first etch wasselectively more rapid in BPSG than in either undoped SiO₂ or nitride.The selectivity of BPSG to nitride therein can also be varied bychanging the concentration of CH₂F₂. A second vertical dry etch havingmore equal nitride and BPSG etch rates is again generally used to clearthe contact region 78. In the Applied Materials 5000 reactor, the recipefor the second etch is: pressure of about 200 mtorr, 600 watts RF power,100 gauss, 50 sccm CF₄, 10 sccm CHF₃, and 9000 mtorr He backsidepressure. These conditions lead to an etch rate of about 57 angstroms ofnitride per second. A usable range for the parameters of the second etchis: pressure of about 100-300 mtorr, 500-700 watts RF power, 60-100gauss (preferably not above 100 gauss), 30-70 sccm CF₄, 5-20 sccm CHF₃,and 4,500-10,000 mtorr He backside pressure. Before performing thesecond dry etch, it may again be useful to substantially clear thenitride layer 84 of polymers by performing the above-described O₂ cleanetch. The combination of high first etch selectivity for BPSG and thebreadloafed reinforcement of the sidewall regions 88 enables the etchesto be completed before a sidewall breach occurs.

[0042] There is alternative etch recipe for the first anisotropic dryetch that is selectively faster in BPSG than nitride. This recipe makesuse of a Lam Research TCP oxide reactor. The Lam device is a highdensity reactor that uses both an upper and lower RF power. Exemplaryconditions for the etch are: pressure of about 3 mtorr, bottom RF powerof 1700 watts, top RF power of 1100 watts, 37 sccm C₂HF₅, 20 sccm CHF₃,20 sccm CH₂F₂, 20 torr He backside pressure. Another LAM Research TCPoxide etch recipe is: pressure of about 5 mtorr, bottom RF power of 1600watts, top RF power of 1500 watts, 20 sccm C₂HF₅, 40 sccm CHF₃, 120 sccmAr, and 20 torr He backside pressure. This second set of conditionsgives an etch rate of about 10,000 angstroms per minute.

[0043] A preferred method to control the second anisotropic dry etch isto monitor for the presence of silicon in the etch gases and terminatewhen a sufficient amount of silicon is detected. The appearance ofsilicon means that the surface of the contact area 78 has been clearedof the nitride layer 84 (undoped oxide layers 66, 70, in the alternateembodiment of FIG. 5). Alternatively, the first dry etch can be timed byits known rates in BPSG and nitride. The relatively high selectivity forBPSG over both nitride and undoped oxide allows one to compensate forirregularities in the thickness of the BPSG layer 74 in estimating thetime for the first dry etch.

[0044] Finally, several methods have been described for constructing andplacing the breadloafed layers 70 and conformal layers 66 that serve asbarriers to dopant contamination from the BPSG layer 74. The describedconstructions have included: a low pressure deposition of breadloafedsilane oxide 70 over a conformal oxide layer 66 formed by the furnacedeposition of TEOS, FIG. 5; a conformal oxide layer 66 formed by furnacedeposition of TEOS over a breadloafed layer 70 formed by low-pressuredeposition of silane oxide; and a single step plasma deposition of abreadloafed layer 84 of nitride, FIG. 8. An alternate construction is a200-300 angstrom thick layer 66 of conformal nitride under a breadloafedupper layer 70 formed by plasma deposition of either silane oxide ornitride. FIG. 5 illustrates this construction, wherein the undoped oxidelayer 66 is formed of nitride, and the breadloafed layer 70 is eitheroxide or nitride. These combinations and others are included within thescope of the present invention under the proviso that one layer gives asufficient dopant barrier during reflow of the BPSG and one layer has abreadloafed form that protects underlying structures from breach duringthe deep dry etching. Making rearrangements and combinations ofbreadloafed and conformal layers, with the above proviso, are within thescope of the present invention and would be routine to workers skilledin the art.

[0045] All of the methods and structures disclosed and claimed hereincan be made and executed without undue experimentation in light of thepresent disclosure. While the compositions and methods of this inventionhave been described in terms of preferred embodiments, it will beapparent to those of skill in the art that variations may be applied tothe structures and in the steps or in the sequence of steps of themethod described herein without departing from the concept, spirit andscope of the invention. All such similar substitutes and modificationsapparent to those skilled in the art are deemed to be within the spirit,scope and concept of the invention as defined by the appended claims.

What is claimed is:
 1. An apparatus, comprising: a semiconductorsubstrate having a contact area on a surface thereof; at least onestructure located on the surface of the substrate adjacent the contactarea; an insulative layer extending over a portion of said structure; alayer of doped oxide extending over at least a portion of saidstructure; and an intermediate layer deposited between said structureand said layer of doped oxide, said intermediate layer having agenerally nonuniform thickness in an area adjacent said structure andbeing resistant to the migration of dopants from said layer of dopedoxide into said structure and substrate.
 2. An apparatus, as set forthin claim 1, wherein said intermediate layer has a generally breadloafedform.
 3. An apparatus, as set forth in claim 1, wherein said structurehas at least one generally vertical surface relative to said substrateand said intermediate layer is thicker adjacent to said vertical surfaceand distant from said substrate.
 4. An apparatus, as set forth in claim1, wherein said intermediate layer includes silicon nitride.
 5. Anapparatus, as set forth in claim 4, wherein said silicon nitride layeris formed by plasma deposition of silane gas in the presence of nitrogengas.
 6. An apparatus, as set forth in claim 1, wherein the structurelocated on the surface of the substrate has a conductive layer.
 7. Anapparatus as set forth in claim 1, wherein the structure located on thesurface of the substrate has a semiconductive layer.
 8. An apparatus asset forth in claim 1, wherein the doped oxide layer is borophososilicateglass.
 9. An apparatus as set forth in claim 1, wherein the insulativelayer is silicon nitride.
 10. An apparatus, as set forth in claim 1,wherein said intermediate layer includes a first and second layer ofundoped oxide extending over at least a portion of said structure, saidfirst layer of undoped oxide having a generally uniform thickness, andsaid second layer of undoped oxide having a generally breadloafed formin an area adjacent said structure.
 11. An apparatus as set forth inclaim 10, wherein the first layer of undoped oxide is located over thesecond layer of undoped oxide.
 12. An apparatus as set forth in claim10, wherein the second layer of undoped oxide is located over the firstlayer of undoped oxide.
 13. An apparatus as set forth in claim 10,wherein the first layer of undoped oxide is an oxide formed by thechemical vapor deposition of tetraethyloxysilane.
 14. An apparatus asset forth in claim 10, wherein the second layer of undoped oxide is anoxide formed by plasma deposition of silane gas in the presence ofnitrous oxide.
 15. An apparatus as set forth in claim 1, wherein theinsulative layer is formed of undoped oxide.
 16. An apparatus, as setforth in claim 1, wherein said intermediate layer includes a layer ofnitride extending over at least a portion of said structure, said layerof nitride having a generally uniform thickness, and a layer of undopedoxide having a generally breadloafed form in an area adjacent saidstructure.
 17. A method for making a semiconductor device, comprisingthe steps of: forming a semiconductor substrate; forming at least onestructure on the surface of said substrate; forming a first insulativelayer over at least a portion of said structure; forming a secondinsulative layer over at least a portion of said structure andsubstrate, said second insulative layer having a generally nonuniformthickness adjacent said structure and being a barrier to the migrationof dopants; and forming a layer of doped oxide over said first andsecond insulative layers.
 18. The method, as set forth in claim 17,wherein the step of forming at least one structure includes forming atleast one structure having a generally vertical surface relative to saidsubstrate and said step of forming a second insulative layer includesforming a layer that is thicker adjacent said vertical surface anddistant from said substrate.
 19. The method, as set forth in claim 17,wherein the step of forming a second insulative layer includes forming alayer having a generally breadloafed form.
 20. The method, as set forthin claim 17, wherein the step of forming the layer of doped oxideincludes forming a layer of borophosphosilicate glass.
 21. The method,as set forth in claim 17, wherein the step of forming a secondinsulative layer includes: forming a first layer of undoped oxide havinga generally uniform thickness; and forming a second layer of undopedoxide having a generally breadloafed form.
 22. The method, as set forthin claim 21, wherein the step of forming the first layer of undopedoxide is performed before the step of forming the second layer ofundoped oxide.
 23. The method, as set forth in claim 21, wherein thestep of forming the second layer of undoped oxide is performed beforethe step of forming the first layer of undoped oxide.
 24. The method, asset forth in claim 21, wherein the step of forming the first layer ofundoped oxide includes performing a chemical vapor deposition oftetraethyloxysilane.
 25. The method, as set forth in claim 21, whereinthe step of forming the second layer of undoped oxide includesperforming a plasma deposition of silane gas in the presence of nitrousoxide.
 26. The method, as set forth in claim 17, wherein the step offorming a second insulative layer includes: first, forming a layer ofsilicon nitride having a generally uniform thickness; and then, forminga layer of undoped oxide having a generally breadloafed form.
 27. Themethod, as set forth in claim 17, wherein the step of forming a secondinsulative layer includes: first, forming a layer of undoped oxidehaving a generally breadloafed form; and then, forming a layer ofsilicon nitride having a generally uniform thickness.
 28. The method, asset forth in claim 17, wherein the step of forming the second insulativelayer includes forming a layer of silicon nitride having a generallybreadloafed form.
 29. The method, as set forth in claim 28, wherein thestep of forming the layer of silicon nitride includes performing aplasma deposition of silane gas in the presence of nitrogen gas.
 30. Themethod, as set forth in claim 17, wherein the step of forming the secondinsulative layer comprises: first, forming a layer of silicon nitridehaving a generally breadloafed form; and then, forming a layer ofundoped oxide having a generally uniform thickness.
 31. The method, asset forth in claim 17, wherein the step of forming the second insulativelayer comprises: first, forming a layer of undoped oxide having agenerally uniform thickness; and then, forming a layer of siliconnitride having a generally breadloafed form.
 32. The method, as setforth in claim 17, wherein the step of forming the first insulativelayer includes forming a layer of silicon nitride.
 33. The method, asset forth in claim 17, wherein the step of forming the first insulativelayer includes forming a layer of undoped oxide.
 34. The method, as setforth in claim 17, wherein the step of forming at least one structureincludes forming a structure with a semiconductive layer.
 35. Anapparatus, comprising: a semiconductor substrate having a contact areaon a surface thereof; at least one structure located on the surface ofthe substrate adjacent the contact area; an insulative layer extendingover at least a portion of said structure; a first layer of undopedoxide extending over at least a portion of said structure and substrate,said first layer of undoped oxide having a generally uniform thickness;a second layer of undoped oxide extending over at least a portion ofsaid structure and substrate, said second layer having a generallybreadloafed form in an area adjacent said structure; and a layer ofdoped oxide extending over at least a portion of said first and secondlayers of undoped oxide.
 36. An apparatus as set forth in claim 35,wherein the first layer of undoped oxide is located over the secondlayer of undoped oxide.
 37. An apparatus as set forth in claim 35,wherein the first layer of undoped oxide is an oxide formed by thechemical vapor deposition of tetraethyloxysilane.
 38. An apparatus asset forth in claim 35, wherein the second layer of undoped oxide is anoxide formed by plasma deposition of silane gas in the presence ofnitrous oxide.
 39. An apparatus as set forth in claim 35, wherein thedoped oxide layer is borophosphosilicate glass.
 40. An apparatus as setforth in claim 35, wherein the insulative layer is silicon nitride. 41.An apparatus as set forth in claim 35, wherein the insulative layer isundoped oxide.
 42. An apparatus, comprising: a semiconductor substratehaving a contact area on a surface thereof; at least one structurelocated on the surface of the substrate adjacent the contact area; aninsulative layer extending over at least a portion of said structure; alayer of silicon nitride extending over at least a portion of saidstructure and of the substrate, said layer having a generallybreadloafed form in an area adjacent said structure; and a layer ofdoped oxide extending over at least a portion of said layer of siliconnitride.
 43. An apparatus as set forth in claim 42, wherein the layer ofsilicon nitride is formed by plasma deposition of silane gas in thepresence of nitrogen gas.
 44. An apparatus as set forth in claim 42,wherein the doped oxide layer is borophosphosilicate glass.
 45. Anapparatus as set forth in claim 42, wherein the insulative layer issilicon nitride.
 46. An apparatus as set forth in claim 42, wherein theinsulative layer is undoped oxide.
 47. An apparatus as set forth inclaim 42, further comprising a layer of undoped oxide having a generallyuniform thickness, extending over at least a portion of said structureand said substrate and being located between said layer of doped oxideand said layer of silicon nitride.
 48. An apparatus as set forth inclaim 42, further comprising a layer of undoped oxide having a generallyuniform thickness, extending over at least a portion of said structureand said substrate and being located between said layer of siliconnitride and said insulative layer.
 49. A method for making asemiconductive device having at least one contact opening therein,comprising the steps of: forming a semiconductor substrate having acontact area; forming at least one structure on a surface of saidsubstrate; forming a conformal layer of undoped oxide over at least aportion of the structure and the substrate; forming a breadloafed layerof undoped oxide over at least a portion of the structure and thesubstrate; forming a layer of doped oxide over the conformal andbreadloafed oxide layers; and etching an opening to the contact area ofthe substrate through the conformal, breadloafed, and doped oxidelayers, said opening being adjacent said structure.
 50. The method, asset forth in claim 49, wherein the step of etching includes performingan anisotropic dry etch having a higher speed in doped oxide than inundoped oxide.
 51. The method, as set forth in claim 50, wherein thestep of performing a dry etch includes applying a fluorinated etchant.52. The method, as set forth in claim 49, wherein the step of etchingcomprises: first, performing a first anisotropic dry etch having ahigher speed in doped oxide than in undoped oxide; and then, performinga second anisotropic dry etch, said second anisotropic dry etch having aspeed in silicon nitride that is, similar or higher than the speed ofsaid second anisotropic dry etch in doped oxide.
 53. The method as setforth in claim 52, further comprising the step of performing an O₂ cleanetch after the step of performing a first anisotropic dry etch andbefore the step of performing a second anisotropic dry etch, said O₂clean etch substantially clearing polymer from, at least, part of theetched surface over the contact area.
 54. The method, as set forth inclaim 49, wherein the step of etching includes: performing ananisotropic dry etch proceeding faster in doped oxide than in undopedoxide for a first preselected period of time; and performing a wet etchhaving a higher speed in undoped oxides than in doped oxides or siliconnitride for a second preselected period of time.
 55. The method, as setforth in claim 49, wherein the step of forming the conformal layer ofundoped oxide layer includes performing a chemical vapor deposition oftetraethyloxysilane.
 56. The method, as set forth in claim 49, whereinthe step of forming the breadloafed layer of undoped oxide includesperforming a plasma deposition of silane gas in the presence of nitrousoxide.
 57. The method, as set forth in claim 49, wherein the step offorming the doped oxide layer includes forming a layer ofborophosphosilicate glass.
 58. The method, as set forth in claim 49,wherein the step of forming a breadloafed layer of undoped oxide isperformed before the step of forming a conformal layer of undoped oxide.59. A method for making a semiconductive device having at least onecontact opening therein, comprising the steps of: forming asemiconductor substrate having a contact area; forming at least onestructure on a surface of said substrate; forming a breadloafed layer ofsilicon nitride over at least a portion of the structure and thesubstrate; forming a layer of doped oxide over the breadloafed layer;and etching an opening through the layers of silicon nitride and dopedoxide layers to the contact area of the substrate, said opening beingadjacent said structure.
 60. The method, as set forth in claim 59,wherein the step of etching includes performing an anisotropic dry etchhaving a higher speed in doped oxide than in nitride.
 61. The method, asset forth in claim 60, wherein the step of performing a dry etchincludes applying a fluorinated etchant.
 62. The method, as set forth inclaim 59, wherein the step of forming the breadloafed layer includesperforming a plasma deposition of silane gas in the presence of nitrogengas.
 63. The method, as set forth in claim 59, wherein the step offorming a doped oxide layer includes forming a layer ofborophosphosilicate glass.
 64. The method, as set forth in claim 59,wherein the step of etching comprises: first, performing a firstanisotropic dry etch having a higher speed in doped oxide than insilicon nitride; and then, performing a second anisotropic dry etch,said second anisotropic dry etch having a speed in silicon nitride thatis, similar or higher than the speed of said second anisotropic dry etchin doped oxide.
 65. The method as set forth in claim 64, furthercomprising the step of performing an O₂ clean etch after the step ofperforming a first anisotropic dry etch and before the step ofperforming a second anisotropic dry etch, said O₂ clean etchsubstantially clearing polymer from, at least, part of the etchedsurface over the contact area.
 66. An apparatus, comprising: asemiconductor substrate having a contact area; at least one structurelocated on the substrate adjacent the contact area; an insulative layerextending over at least a portion of said structure; a first layer ofundoped oxide extending over at least a portion of said structure, saidlayer of undoped oxide having a generally uniform thickness; a secondlayer of undoped oxide extending over at least a portion of saidstructure, said second layer having a generally breadloafed form in anarea adjacent said structure; a layer of doped oxide extending over atleast a portion of said first and second undoped oxide layers; and aconductive layer extending over at least a portion of the contact areaof said substrate, the first and second undoped oxide layers, theinsulative layer, the doped oxide layer, and the structure and being inelectrical contact with the contract area of the substrate and insulatedfrom electrical contact with the structure.
 67. An apparatus as setforth in claim 66, wherein the insulative layer is comprised of siliconnitride.
 68. An apparatus as set forth in claim 66, wherein theinsulative layer is comprised of undoped oxide.
 69. An apparatus as setforth in claim 66, wherein the first layer of undoped oxide is locatedover the second layer of undoped oxide.
 70. An apparatus as set forth inclaim 66, wherein the doped oxide is borophosphosilicate glass.
 71. Anapparatus as set forth in claim 66, wherein the first layer of undopedoxide is comprised of an oxide formed by the chemical vapor depositionof tetraethyloxysilane.
 72. An apparatus as set forth in claim 66,wherein the second layer of undoped oxide is an oxide formed by plasmadeposition of silane gas in the presence of nitrous oxide.
 73. Anapparatus, comprising: a semiconductor substrate having a contact areaon a surface thereof; at least one structure located on the surface ofthe substrate adjacent the contact area; an insulative layer extendingover at least a portion of said structure; a layer of silicon nitrideextending over at least a portion of said structure, said layer having agenerally breadloafed form in an area adjacent said structure; a layerof doped oxide extending over at least a portion of said layer ofsilicon nitride; and a conductive layer extending over the at least aportion of the contact area of said substrate, the insulative layer, thelayer of silicon nitride, and the doped oxide layer and being inelectrical contact with the contact area of the substrate and insulatedfrom electrical contact with the structure.
 74. An apparatus as setforth in claim 73, wherein the layer of silicon nitride is the layerformed by plasma deposition of silane gas in the presence of nitrogengas.
 75. An apparatus as set forth in claim 73, wherein the doped oxidelayer is borophosphosilicate glass.
 76. An apparatus as set forth inclaim 73, wherein the insulative layer is silicon nitride.
 77. Anapparatus as set forth in claim 73, wherein the insulative layer isundoped oxide.
 78. An apparatus as set forth in claim 73, furthercomprising a layer of undoped oxide having a generally uniformthickness, extending over at least a portion of said structure and saidsubstrate and being located between said layer of doped oxide and saidlayer of silicon nitride.
 79. An apparatus as set forth in claim 73,further comprising a layer of undoped oxide having a generally uniformthickness, extending over at least a portion of said structure and saidsubstrate and being located between said layer of silicon nitride andsaid insulative layer.